Title: CNT and CNW nano structures growth on SiC wafer surfaces

Biography:

Dr. Brahm Pal Singh completed his Ph. D. in Quantum Electronics, (1990), IIT Delhi; his D. Eng. in Quantum Engineering (1996), Nagoya University with Postdoctoral Research Studies at NPL, India and AIST Tsukuba, Japan. Dr. Singh is the R & D Manager in Advanced Technologies Development Center, ES Company, Panasonic Corporation. He has published over 30 research papers in reputed international journals and conferences/symposiums and serving as a referee for the reputed international journal

Abstract

The chemical mechanical polished (4H and 6H) SiC wafers were heated in the range of 1700-2000oC putting on a flat surface of a pyrolytic graphite plate in the graphite vacuum furnace of a pyrolytic surrounded by a cylindrical internal graphite chamber (Diameter = 130 mm and height = 100 mm) having an opening in its top surface center. For the selective CNS layer growth on the SiC wafer size ranging from 8 x 8 mm2 to 50.8 mm diameter, the wafer was enclosed in a pyrolytic graphite case exposing the regions on its desired face only where CNS was to be grown. The SiC wafer heating was done using a computer controlled electric heater with an accuracy of 1oC in the vacuum pressure of <2x10-4 Torr. The thermal heating recipe was prepared so that the SiC wafer was thermally cleaned for 10 min at 1200oC before reaching the thermally decomposition temperature in the range of 1700-2000oC at a rate of 15oC/min. The heating temperature was maintained for the desired CNS layer thickness growth before switching off the heater to let the sample cool down to the room temperature while the vacuum pump was kept continuously ON